(1) Field of the Invention
The invention relates to a method of analyzing the structure of multilayer interconnectors in the fabrication of integrated circuits, and more particularly, to a method of revealing three dimensional structures in analyzing the structure of multilayer interconnections in the manufacture of integrated circuits.
(2) Description of the Prior Art
Successful integrated circuit device manufacture requires continued monitoring of the results of the fabrication processes. Monitoring may be performed visually or by using tools such as the Scanning Electron Microscope (SEM). Defects or problems in the manufacturing process then can be detected and corrected.
It is difficult to inspect three-dimensional structures of multilayer interconnections, such as 3 or 4 layers. Typically, the wafer is prepared for analysis by SEM by removing the interlevel dielectric layers adjacent to the interconnection area to be observed. When the sidewall structure is exposed, the SEM analysis can be performed. Conventionally, the interlevel dielectric layers are removed by reactive ion etching (RIE) or by wet etching. RIE has poor selectivity to metal connectors so that some of the metal is removed during the removal of the interlevel dielectric layers. Also, a dielectric layer underlying metal interconnectors cannot be removed completely by RIE. When the dielectric layers are removed by wet etching, the etching time must be long enough to remove the bottom dielectric layer. This etching time is so long that the top metal lines may be lifted off.
U.S. Pat. No. 4,900,695 to Takahashi et al shows a method of using a focused ion beam to etch out a portion of an insulating layer. U.S. Pat. No. 5,028,780 to Kaito et al teaches a method of preparing microsections for analysis by first depositing a film to planarize the section, then using a focused ion beam to etch a rectangular groove for observation. U.S. Pat. No. 5,583,344 to Mizumura et al teaches a method and an apparatus for using a focused ion beam to prepare a wafer for analysis in which the substances emitted from the ion source do not contaminate the wafer for further processing.